Design Rule Verification Report
Date:
2/28/2025
Time:
12:56:17 PM
Elapsed Time:
00:00:00
Filename:
C:\Users\jd106363\OneDrive - Qorvo\Documents\Altium Files\ACT72350\ACT72350SAEVK1_RevA.PcbDoc
Warnings:
0
Rule Violations:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=26.575mil) (not InNetClass('HV_W') and not InComponentClass('HV_Exclude')),(InNetClass('HV_W') and not InComponentClass('HV_Exclude'))
0
Clearance Constraint (Gap=26.575mil) (not InNetClass('HV_VM') and not InComponentClass('HV_Exclude')),(InNetClass('HV_VM') and not InComponentClass('HV_Exclude'))
0
Clearance Constraint (Gap=26.575mil) (not InNetClass('HV_V') and not InComponentClass('HV_Exclude')),(InNetClass('HV_V') and not InComponentClass('HV_Exclude'))
0
Clearance Constraint (Gap=8mil) (All),(All)
0
Clearance Constraint (Gap=26.575mil) (not InNetClass('HV_U') and not InComponentClass('HV_Exclude')),(InNetClass('HV_U') and not InComponentClass('HV_Exclude'))
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All)
0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
0
Minimum Annular Ring (Minimum=5mil) (All)
0
Hole Size Constraint (Min=10mil) (Max=246mil) (All)
0
Hole To Hole Clearance (Gap=8mil) (All),(All)
0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)
0
Silk to Silk (Clearance=0mil) (All),(All)
0
Net Antennae (Tolerance=50mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Total
0
