Altium

Design Rule Verification Report

Date: 5/1/2025
Time: 3:01:00 PM
Elapsed Time: 00:00:00
Filename: C:\Users\jd106363\OneDrive - Qorvo\Documents\PAC5XXX Documentation\PAC5556AEVK2_RevB\PAC5556AEVK2_RevB\PAC5556AEVK2_RevB.PcbDoc
Warnings: 0
Rule Violations: 2

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=1.27mm) (OnLayer('Keep-Out Layer')),(All) 2
Clearance Constraint (Gap=1.7mm) (not InNetClass('HV_U') and not InComponentClass('HV_Exclude')),(InNetClass('HV_U') and not InComponentClass('HV_Exclude')) 0
Clearance Constraint (Gap=0.203mm) (All),(All) 0
Clearance Constraint (Gap=1.25mm) (not InNetClass('HV_VM') and not InComponentClass('HV_Exclude')),(InNetClass('HV_VM') and not InComponentClass('HV_Exclude')) 0
Clearance Constraint (Gap=1.7mm) (not InNetClass('HV_V') and not InComponentClass('HV_Exclude')),(InNetClass('HV_V') and not InComponentClass('HV_Exclude')) 0
Clearance Constraint (Gap=1.75mm) (not InNetClass('HV_VAC') and not InComponentClass('HV_Exclude')),(InNetClass('HV_VAC') and not InComponentClass('HV_Exclude')) 0
Clearance Constraint (Gap=1.75mm) (not InNetClass('HV_VAC2') and not InComponentClass('HV_Exclude')),(InNetClass('HV_VAC2') and not InComponentClass('HV_Exclude')) 0
Clearance Constraint (Gap=1.7mm) (not InNetClass('HV_W') and not InComponentClass('HV_Exclude')),(InNetClass('HV_W') and not InComponentClass('HV_Exclude')) 0
Clearance Constraint (Gap=1.75mm) (not InNetClass('HV_VBUS') and not InComponentClass('HV_Exclude')),(InNetClass('HV_VBUS') and not InComponentClass('HV_Exclude')) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=0.152mm) (Max=2.54mm) (Preferred=0.254mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.127mm) (All) 0
Hole Size Constraint (Min=0.305mm) (Max=6.248mm) (All) 0
Hole To Hole Clearance (Gap=0.203mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All) 0
Silk To Solder Mask (Clearance=0mm) (IsPad),(All) 0
Silk to Silk (Clearance=0mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Height Constraint (Min=0mm) (Max=2539.975mm) (Prefered=12.7mm) (All) 0
Total 2

Clearance Constraint (Gap=1.27mm) (OnLayer('Keep-Out Layer')),(All)
Clearance Constraint: (1.193mm < 1.27mm) Between Arc (47.053mm,124.379mm) on Keep-Out Layer And Text "SIG1 LAYER" (43.358mm,127.813mm) on SIG1
Clearance Constraint: (1.015mm < 1.27mm) Between Arc (98.974mm,124.379mm) on Keep-Out Layer And Text "TOP LAYER" (93.345mm,127.635mm) on Top Layer

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